PIC16F631/677/685/687/689/690
FIGURE 2-3:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F677/PIC16F687
2.2
Data Memory Organization
The data memory (see Figures 2-6 through 2-8) is
partitioned into four banks which contain the General
Purpose Registers (GPR) and the Special Function
Registers (SFR). The Special Function Registers are
located in the first 32 locations of each bank. The
General Purpose Registers, implemented as static
RAM, are located in the last 96 locations of each Bank.
Register locations F0h-FFh in Bank 1, 170h-17Fh in
Bank 2 and 1F0h-1FFh in Bank 3 point to addresses
70h-7Fh in Bank 0. The actual number of General
Purpose Resisters (GPR) in each Bank depends on the
device. Details are shown in Figures 2-4 through 2-8.
All other RAM is unimplemented and returns ‘0’ when
read. RP<1:0> of the STATUS register are the bank
select bits:
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
RP1
0
RP0
0
0004h
0005h
Interrupt Vector
→
→
→
→
Bank 0 is selected
Bank 1 is selected
Bank 2 is selected
Bank 3 is selected
0
1
On-chip Program
Memory
1
0
1
1
07FFh
0800h
2.2.1
GENERAL PURPOSE REGISTER
FILE
Access 0-7FFh
The register file is organized as 128 x 8 in the
PIC16F687 and 256 in the
1FFFh
x
8
PIC16F685/PIC16F689/PIC16F690. Each register is
accessed, either directly or indirectly, through the File
Select Register (FSR) (see Section 2.4 “Indirect
Addressing, INDF and FSR Registers”).
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Tables 2-1
through 2-4). These registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Registers related to the operation of peripheral features
are described in the section of that peripheral feature.
DS41262D-page 26
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
