PIC16F72X/PIC16LF72X
TABLE 1:
28-Pin
PDIP,
SOIC,
SSOP
2
3
4
5
6
7
10
9
21
22
23
24
25
26
27
28
11
12
13
14
15
16
17
18
1
20
8,19
1:
2:
3:
4:
28-PIN PDIP/SOIC/SSOP/QFN/UQFN SUMMARY
(PIC16F722/723/726/PIC16LF722/723/726)
28-Pin
QFN,
UQFN
27
28
1
2
3
4
7
6
18
19
20
21
22
23
24
25
8
9
10
11
12
13
14
15
26
17
5,16
A/D
Cap Sensor
Timers
CCP
AUSART
SSP
Interrupt Pull-Up
Basic
I/O
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RE3
—
—
Note
AN0
AN1
AN2
AN3/V
REF
—
AN4
—
—
AN12
AN10
AN8
AN9
AN11
AN13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CPS6
CPS7
—
—
CPS0
CPS1
CPS2
CPS3
CPS4
CPS5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T0CKI
—
—
—
—
—
—
—
—
T1G
—
—
T1OSO/T1CKI
T1OSI
—
—
—
—
—
—
—
—
—
—
—
—
—
CCP2
(2)
—
—
—
—
—
CCP2
(2)
CCP1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TX/CK
RX/DT
—
—
—
SS
(3)
—
—
—
—
SS
(3)
—
—
—
—
—
—
—
—
—
—
—
—
—
SCK/SCL
SDI/SDA
SDO
—
—
—
—
—
—
—
—
—
—
—
—
—
IOC/INT
IOC
IOC
IOC
IOC
IOC
IOC
IOC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
Y
Y
Y
Y
Y
Y
Y
—
—
—
—
—
—
—
—
Y
(1)
—
—
V
CAP
(4)
—
—
—
—
V
CAP
(4)
OSC2/CLKOUT/V
CAP
(4)
OSC1/CLKIN
—
—
—
—
—
—
ICSPCLK/ICDCLK
ICSPDAT/ICDDAT
—
—
—
—
—
—
—
—
MCLR/V
PP
V
DD
V
SS
—
—
—
—
—
—
—
—
—
—
—
—
Pull-up enabled only with external MCLR configuration.
RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.
RA5 is the default pin location for SS. RA0 may be selected by changing the SSSEL bit in the APFCON register.
PIC16F72X devices only.
Note:
The PIC16F72X devices have an internal low dropout voltage regulator. An external capacitor must be
connected to one of the available V
CAP
pins to stabilize the regulator. For more information, see
The PIC16LF72X devices do not have the voltage
regulator and therefore no external capacitor is required.
DS41341E-page 6
©
2009 Microchip Technology Inc.