PIC16F72X/PIC16LF72X
6.0
I/O PORTS
There are as many as thirty-five general purpose I/O
pins available. Depending on which peripherals are
enabled, some or all of the pins may not be available as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
6.1
Alternate Pin Function
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 6-1. For this device family, the
following functions can be moved between different
pins.
• SS (Slave Select)
• CCP2
REGISTER 6-1:
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-2
bit 1
APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SSSEL
R/W-0
CCP2SEL
bit 0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented:
Read as ‘0’.
SSSEL:
SS Input Pin Selection bit
0
= SS function is on RA5/AN4/CPS7/SS/V
CAP
1
= SS function is on RA0/AN0/SS/V
CAP
CCP2SEL:
CCP2 Input/Output Pin Selection bit
0
= CCP2 function is on RC1/T1OSI/CCP2
1
= CCP2 function is on RB3/CCP2
bit 0
©
2009 Microchip Technology Inc.
DS41341E-page 53
MICROCHIP [ MICROCHIP TECHNOLOGY ]
