PIC16F72X/PIC16LF72X
16.0
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
The AUSART module includes the following capabilities:
•
•
•
•
•
•
•
•
•
•
Full-duplex asynchronous transmit and receive
Two-character input buffer
One-character output buffer
Programmable 8-bit or 9-bit character length
Address detection in 9-bit mode
Input buffer overrun error detection
Received character framing error detection
Half-duplex synchronous master
Half-duplex synchronous slave
Sleep operation
The
Addressable
Universal
Synchronous
Asynchronous Receiver Transmitter (AUSART)
module is a serial I/O communications peripheral. It
contains all the clock generators, shift registers and
data buffers necessary to perform an input or output
serial data transfer independent of device program
execution. The AUSART, also known as a Serial
Communications Interface (SCI), can be configured as
a full-duplex asynchronous system or half-duplex
synchronous system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
Block diagrams of the AUSART transmitter and
receiver are shown in Figure 16-1 and Figure 16-2.
FIGURE 16-1:
AUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIE
Interrupt
TXREG Register
8
MSb
(8)
LSb
TX/CK
Pin Buffer
and Control
TXIF
• • •
Transmit Shift Register (TSR)
0
TXEN
Baud Rate Generator
TRMT
F
OSC
÷n
n
+1
Multiplier
SYNC
SPBRG
BRGH
x4
1
x
x16 x64
0
1
0
0
TX9D
TX9
SPEN
©
2009 Microchip Technology Inc.
DS41341E-page 145
MICROCHIP [ MICROCHIP TECHNOLOGY ]
