PIC16F688
FIGURE 7-2:
COMPARATOR C1 OUTPUT BLOCK DIAGRAM
C1INV
To C1OUT pin
To Data Bus
C1
D
Q
Q
Q1
EN
RD CMCON0
Set C1IF bit
D
Q3*RD CMCON0
EN
CL
Reset
Note 1: Q1 and Q3 are phases of the four-phase system clock (FOSC).
2: Q1 is held high during Sleep mode.
FIGURE 7-3:
COMPARATOR C2 OUTPUT BLOCK DIAGRAM
C2SYNC
To Timer1 Gate
To C2OUT pin
C2INV
0
1
C2
D
Q
Timer1
clock source
(1)
To Data Bus
Set C2IF bit
D
Q
Q
Q1
EN
RD CMCON0
D
Q3*RD CMCON0
EN
CL
Reset
Note 1: Comparator output is latched on falling edge of Timer1 clock source.
2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.
DS41203D-page 54
© 2007 Microchip Technology Inc.