PIC16F631/677/685/687/689/690
FIGURE 1-4:
PIC16F687/PIC16F689 BLOCK DIAGRAM
INT
Configuration
13
8
PORTA
Data Bus
Program Counter
Flash
2K(1)/4K x 14
Program
RA0
RA1
RA2
RA3
RA4
RA5
RAM
128(1)/256 bytes
File
8-Level Stack (13-bit)
Memory
Registers
Program
Bus
14
RAM Addr
9
PORTB
Addr MUX
Instruction Reg
Indirect
Addr
7
RB4
Direct Addr
8
RB5
RB6
RB7
FSR Reg
STATUS Reg
8
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
3
MUX
Power-up
Timer
Instruction
Decode and
Control
Oscillator
Start-up Timer
ALU
OSC1/CLKI
OSC2/CLKO
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
W Reg
Brown-out
Reset
Internal
Oscillator
Block
VDD
VSS
MCLR
SDI/ SCK/
SDA SCL
SS
SDO
TX/CK
RX/DT
T0CKI
T1G T1CKI
ULPWU
Ultra Low-Power
Wake-up
Synchronous
Serial Port
EUSART
Timer0
Timer1
AN8 AN9 AN10 AN11
EEDAT
256 Bytes
Data
EEPROM
8
2
Analog Comparators
and Reference
Analog-To-Digital Converter
EEADR
VREF
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
Note 1: PIC16F687 only.
DS41262D-page 12
© 2007 Microchip Technology Inc.