PIC16F631/677/685/687/689/690
FIGURE 14-8:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(3)
CLKOUT
(4)
INT pin
(1)
(1)
(2)
(5)
Interrupt Latency
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC + 1
—
0004h
0005h
PC
Inst (PC)
PC + 1
Instruction
Fetched
Inst (PC + 1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC – 1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 17.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 14-6: SUMMARY OF INTERRUPT REGISTERS
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
INTCON
PIE1
GIE
—
PEIE
ADIE
C2IE
ADIF
C2IF
T0IE
RCIE
C1IE
RCIF
C1IF
INTE
TXIE
EEIE
TXIF
EEIF
RABIE
SSPIE
—
T0IF
INTF
RABIF
0000 000x 0000 000x
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
0000 ---- 0000 ----
CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
0000 ---- 0000 ----
PIE2
OSFIE
—
—
—
—
PIR1
SSPIF
—
PIR2
OSFIF
—
—
—
Legend:
x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends upon condition.
Shaded cells are not used by the Interrupt module.
DS41262D-page 206
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
