PIC16F631/677/685/687/689/690
REGISTER 13-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER(1)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
(2)
(2)
(2)
(2)
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
WCOL: Write Collision Detect bit
1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0= No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the
data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only
transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new recep-
tion (and transmission) is initiated by writing to the SSPBUF register.
0= No overflow
2
In I C™ mode:
1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in
Transmit mode. SSPOV must be cleared in software in either mode.
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
1= Enables serial port and configures SCK, SDO and SDI as serial port pins
0= Disables serial port and configures these pins as I/O port pins
2
In I C mode:
1= Enables the serial port and configures the SDA and SCL pins as serial port pins
0= Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= Idle state for clock is a high level (Microwire default)
0= Idle state for clock is a low level (Microwire alternate)
2
In I C mode:
SCK release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
2
0110= I C Slave mode, 7-bit address
2
0111= I C Slave mode, 10-bit address
1000= Reserved
1001= Load SSPMSK register at SSPADD SFR address
(2)
1010= Reserved
2
1011= I C Firmware Controlled Master mode (slave IDLE)
1100= Reserved
1101= Reserved
2
1110= I C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
2
1111= I C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note 1: PIC16F687/PIC16F689/PIC16F690 only.
2: When this mode is selected, any reads or writes to the SSPADD SFR address actually accesses the SSPMSK register.
© 2007 Microchip Technology Inc.
DS41262D-page 177
MICROCHIP [ MICROCHIP ]
