PIC16F631/677/685/687/689/690
FIGURE 1-3:
PIC16F685 BLOCK DIAGRAM
INT
Configuration
13
8
PORTA
Data Bus
Program Counter
Flash
RA0
RA1
RA2
RA3
RA4
RA5
4K x 14
Program
Memory
RAM
256 bytes
File
8-Level Stack (13-bit)
Registers
Program
Bus
14
RAM Addr
9
PORTB
Addr MUX
Instruction Reg
Indirect
Addr
RB4
RB5
7
Direct Addr
8
RB6
RB7
FSR Reg
STATUS Reg
MUX
8
PORTC
RC0
RC1
3
Power-up
Timer
RC2
RC3
RC4
RC5
RC6
RC7
Instruction
Decode and
Control
Oscillator
Start-up Timer
ALU
OSC1/CLKI
OSC2/CLKO
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
W Reg
Brown-out
Reset
Internal
Oscillator
Block
VDD VSS
MCLR
CCP1/
P1A P1B P1C P1D
T0CKI
T1G T1CKI
ULPWU
Ultra Low-Power
Wake-up
Timer2
Timer0
Timer1
ECCP+
AN8 AN9 AN10 AN11
EEDAT
256 Bytes
Data
EEPROM
8
2
Analog Comparators
and Reference
Analog-To-Digital Converter
EEADR
VREF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
© 2007 Microchip Technology Inc.
DS41262D-page 11
MICROCHIP [ MICROCHIP ]
