PIC16F631/677/685/687/689/690
11.2.2
TIMER1 MODE SELECTION
11.2 Compare Mode
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP module may:
• Toggle the CCP1 output
• Set the CCP1 output
11.2.3
SOFTWARE INTERRUPT MODE
• Clear the CCP1 output
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP module does not
assert control of the CCP1 pin (see the CCP1CON
register).
• Generate a Special Event Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCP1M<3:0> control bits of the CCP1CON register.
11.2.4
SPECIAL EVENT TRIGGER
All Compare modes can generate an interrupt.
When Special Event Trigger mode is chosen
(CCP1M<3:0> = 1011), the CCP module does the
following:
FIGURE 11-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
CCP1CON<3:0>
Mode Select
The CCP module does not assert control of the CCP1
pin in this mode (see the CCP1CON register).
Set CCP1IF Interrupt Flag
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPR1H, CCPR1L
register pair. The TMR1H, TMR1L register pair is not
reset until the next rising edge of the Timer1 clock. This
allows the CCPR1H, CCPR1L register pair to
effectively provide a 16-bit programmable period
register for Timer1.
(PIR1)
4
CCP1
Pin
CCPR1H CCPR1L
Comparator
Q
S
R
Output
Logic
Match
TMR1H TMR1L
TRIS
Output Enable
Special Event Trigger
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMR1IF of the PIR1 register.
Special Event Trigger will:
•
•
•
Clear TMR1H and TMR1L registers.
NOT set interrupt flag bit TMR1IF of the PIR1 register.
Set the GO/DONE bit to start the ADC conversion.
2: Removing the match condition by
changing the contents of the CCPR1H
and CCPR1L register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will preclude
the Reset from occurring.
11.2.1
CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the associated TRIS bit.
Note:
Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the port I/O
data latch.
© 2007 Microchip Technology Inc.
DS41262D-page 129
MICROCHIP [ MICROCHIP ]
