PIC16F631/677/685/687/689/690
TABLE 17-14: I2C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
100 kHz mode
Min
Max Units
Conditions
100*
THIGH
Clock high time
4.0
—
—
μs
μs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
Device must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
4.7
—
—
101*
TLOW
Clock low time
100 kHz mode
μs
μs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
SSP Module
1.3
—
Device must operate at a
minimum of 10 MHz
1.5TCY
—
—
102*
103*
TR
TF
SDA and SCL rise 100 kHz mode
time
1000
ns
ns
400 kHz mode
20 + 0.1CB 300
CB is specified to be from
10-400 pF
SDA and SCL fall
time
100 kHz mode
400 kHz mode
—
300
ns
ns
20 + 0.1CB 300
CB is specified to be from
10-400 pF
90*
91*
TSU:STA Start condition
setup time
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
μs
μs
μs
μs
ns
μs
ns
ns
μs
μs
ns
ns
μs
μs
Only relevant for
Repeated Start condition
THD:STA Start condition hold 100 kHz mode
—
After this period the first
clock pulse is generated
time
400 kHz mode
—
106*
107*
92*
THD:DAT Data input hold time 100 kHz mode
400 kHz mode
—
0
0.9
—
TSU:DAT Data input setup
time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
(Note 2)
—
TSU:STO Stop condition
setup time
—
—
109*
110*
TAA
Output valid from
clock
3500
—
(Note 1)
—
TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
CB
Bus capacitive loading
—
400
pF
*
These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it
must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.
© 2007 Microchip Technology Inc.
DS41262D-page 251
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