PIC16F630/676
TABLE 9-8:
SUMMARY OF INTERRUPT REGISTERS
Value on all
other
RESETS
Value on
POR, BOD
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh INTCON
GIE
EEIF
EEIE
PEIE
ADIF
ADIE
T0IE
—
INTE
—
RAIE
CMIF
CMIE
T0IF
—
INTF
—
RAIF
0000 0000 0000 000u
0Ch
8Ch
PIR1
PIE1
TMR1IF 00-- 0--0 00-- 0--0
TMR1IE 00-- 0--0 00-- 0--0
—
—
—
—
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
Shaded cells are not used by the Interrupt module.
9.5
Context Saving During Interrupts
9.6
Watchdog Timer (WDT)
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W register and
STATUS register). This must be implemented in
software.
The Watchdog Timer is a free running, on-chip RC
oscillator, which requires no external components. This
RC oscillator is separate from the external RC oscillator
of the CLKIN pin. That means that the WDT will run,
even if the clock on the OSC1 and OSC2 pins of the
device has been stopped (for example, by execution of
a SLEEPinstruction). During normal operation, a WDT
time-out generates a device RESET. If the device is in
SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the
configuration bit WDTE as clear (Section 9.1).
Example 9-2 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined
at 0x20 in Bank 0 and it must also be defined at 0xA0
in Bank 1). The user register, STATUS_TEMP, must be
defined in Bank 0. The Example 9-2:
• Stores the W register
9.6.1
WDT PERIOD
• Stores the STATUS register in Bank 0
• Executes the ISR code
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
• Restores the STATUS (and bank select bit
register)
• Restores the W register
EXAMPLE 9-2:
SAVING THE STATUS AND
W REGISTERS IN RAM
;copy W to temp register,
could be in either bank
;swap status to be saved into W
;change to bank 0 regardless of
current bank
MOVWF W_TEMP
The CLRWDTand SLEEPinstructions clear the WDT
and the prescaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
SWAPF STATUS,W
BCF
STATUS,RP0
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
MOVWF STATUS_TEMP ;save status to bank 0 register
:
:(ISR)
:
9.6.2
WDT PROGRAMMING
CONSIDERATIONS
SWAPF STATUS_TEMP,W;swap STATUS_TEMP register into
W, sets bank to original state
MOVWF STATUS
SWAPF W_TEMP,F
SWAPF W_TEMP,W
;move W into STATUS register
;swap W_TEMP
;swap W_TEMP into W
It should also be taken in account that under worst case
conditions (i.e., VDD = Min., Temperature = Max., Max.
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
DS40039E-page 66
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
