PIC16F630/676
FIGURE 12-11:
PIC16F676 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
134
(1)
(TOSC/2 + TCY)
1 TCY
131
Q4
130
A/D CLK
9
8
7
3
2
1
0
6
A/D DATA
NEW_DATA
1 TCY
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
132
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 12-10: PIC16F676 A/D CONVERSION REQUIREMENTS (SLEEP MODE)
Param
Sym
Characteristic
Min
Typ†
Max Units
Conditions
No.
130
TAD
A/D Clock Period
1.6
—
—
—
—
μs VREF ≥ 3.0V
μs VREF full range
ADCS<1:0> = 11(RC mode)
μs At VDD = 2.5V
3.0*
130
TAD
A/D Internal RC
Oscillator Period
3.0*
2.0*
—
6.0
4.0
11
9.0*
6.0*
—
μs At VDD = 5.0V
131
132
TCNV
TACQ
Conversion Time
(not including
TAD
Acquisition Time)(1)
Acquisition Time
(Note 2)
11.5
—
—
—
μs
5*
μs The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1 LSb (i.e.,
4.1 mV @ 4.096V) from the last
sampled voltage (as stored on
CHOLD).
134
TGO
Q4 to A/D Clock
Start
—
TOSC/2 + TCY
—
—
If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEPinstruction to be
executed.
*
These parameters are characterized but not tested.
†
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Table 7-1 for minimum conditions.
© 2007 Microchip Technology Inc.
DS40039E-page 103
MICROCHIP [ MICROCHIP ]
