PIC12F508/509/16F505
FIGURE 3-1:
PIC12F508/509 BLOCK DIAGRAM
12
8
GPIO
Data Bus
Program Counter
Flash
GP0/ISCPDAT
GP1/ISCPCLK
GP2/T0CKI
GP3/MCLR/VPP
GP4/OSC2
512 x 12 or
1024 x 12
RAM
Program
Memory
25 x 8 or
Stack 1
Stack 2
File
Registers
GP5/OSC1/CLKIN
Program
Bus
12
RAM Addr
9
Addr MUX
Instruction Reg
Indirect
Addr
5
Direct Addr
5-7
FSR Reg
Status Reg
8
3
MUX
Device Reset
Timer
Instruction
Decode &
Control
ALU
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
OSC1/CLKIN
OSC2
W Reg
Internal RC
OSC
Timer0
MCLR
VDD, VSS
DS41236C-page 10
Preliminary
© 2007 Microchip Technology Inc.