PIC16C62X
4.2.2
SPECIAL FUNCTION REGISTERS
The special function registers are registers used by the
CPU and Peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The special function registers
associated with the “core” functions are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
TABLE 4-1:
Address Name
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
SPECIAL REGISTERS FOR THE PIC16C62X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR Reset
Value on all
other
resets
(1)
Addressing this location uses contents of FSR to address data memory (not a physical
register)
Timer0 Module’s Register
Program Counter's (PC) Least Significant Byte
IRP
(2)
RP1
(2)
RP0
TO
PD
Z
DC
C
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
0000 0000
000q quuu
uuuu uuuu
---u 0000
uuuu uuuu
—
—
—
---0 0000
0000 000u
-0-- ----
—
00-- 0000
Indirect data memory address pointer
—
RB7
—
RB6
—
RB5
RA4
RB4
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0
---x 0000
xxxx xxxx
—
—
—
Unimplemented
Unimplemented
Unimplemented
PCLATH
INTCON
PIR1
—
GIE
—
—
PEIE
CMIF
—
T0IE
—
Write buffer for upper 5 bits of program counter
INTE
—
RBIE
—
T0IF
—
INTF
—
RBIF
—
---0 0000
0000 000x
-0-- ----
—
0Dh-1Eh Unimplemented
1Fh
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh-9Eh
9Fh
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
Unimplemented
Unimplemented
Unimplemented
PCLATH
INTCON
PIE1
Unimplemented
PCON
Unimplemented
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
—
—
—
—
—
—
POR
BOR
—
GIE
—
—
PEIE
CMIE
—
T0IE
—
Write buffer for upper 5 bits of program counter
INTE
—
RBIE
—
T0IF
—
INTF
—
RBIF
—
Addressing this location uses contents of FSR to address data memory (not a physical
register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
CMCON
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000
xxxx xxxx
1111 1111
0000 0000
xxxx xxxx
1111 1111
0000 0000
000q quuu
uuuu uuuu
---1 1111
1111 1111
—
—
—
---0 0000
0000 000u
-0-- ----
—
---- --uq
—
000- 0000
Program Counter's (PC) Least Significant Byte
IRP
(2)
RP1
(2)
RP0
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
Indirect data memory address pointer
—
TRISB7
—
TRISB6
—
TRISB5
TRISA4
TRISB4
TRISA3
TRISB3
TRISA2
TRISB2
TRISA1
TRISB1
TRISA0
TRISB0
---1 1111
1111 1111
—
—
—
---0 0000
0000 000x
-0-- ----
—
---- --0x
—
000- 0000
Legend:
—
= Unimplemented locations read as ‘0’,
u
= unchanged,
x
= unknown,
q
= value depends on condition,
shaded = unimplemented
Note 1:
Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during
normal operation.
Note 2:
IRP & RPI bits are reserved, always maintain these bits clear.
©
1998 Microchip Technology Inc.
Preliminary
DS30235G-page 17
MICROCHIP [ MICROCHIP TECHNOLOGY ]
