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PIC16F870-I/SS 参数 Datasheet PDF下载

PIC16F870-I/SS图片预览
型号: PIC16F870-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚8位CMOS闪存微控制器 [28/40-Pin 8-Bit CMOS FLASH Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路装置光电二极管PC时钟
文件页数/大小: 156 页 / 2816 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F870/871  
WDT time-out period values may be found in the Elec-  
trical Specifications section under parameter #31. Val-  
ues for the WDT prescaler (actually a postscaler, but  
shared with the Timer0 prescaler) may be assigned  
using the OPTION_REG register.  
11.12 Watchdog Timer (WDT)  
The Watchdog Timer is as a free running on-chip RC  
oscillator which does not require any external compo-  
nents. This RC oscillator is separate from the RC oscil-  
lator of the OSC1/CLKIN pin. That means that the WDT  
will run, even if the clock on the OSC1/CLKIN and  
OSC2/CLKOUT pins of the device has been stopped,  
for example, by execution of a SLEEPinstruction.  
Note: The CLRWDTand SLEEPinstructions clear  
the WDT and the postscaler, if assigned to  
the WDT, and prevent it from timing out and  
generating a device RESET condition.  
During normal operation, a WDT time-out generates a  
device RESET (Watchdog Timer Reset). If the device is  
in SLEEP mode, a WDT time-out causes the device to  
wake-up and continue with normal operation (Watch-  
dog Timer Wake-up). The TO bit in the STATUS register  
will be cleared upon a Watchdog Timer time-out.  
.
Note: When a CLRWDT instruction is executed  
and the prescaler is assigned to the WDT,  
the prescaler count will be cleared, but the  
prescaler assignment is not changed.  
The WDT can be permanently disabled by clearing  
configuration bit WDTE (Section 11.1).  
FIGURE 11-10: WATCHDOG TIMER BLOCK DIAGRAM  
From TMR0 Clock Source  
(Figure 5-1)  
0
Postscaler  
8
M
1
U
WDT Timer  
X
8 - to - 1 MUX  
PS2:PS0  
PSA  
WDT  
Enable Bit  
To TMR0 (Figure 5-1)  
0
1
MUX  
PSA  
WDT  
Time-out  
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.  
FIGURE 11-11: SUMMARY OF WATCHDOG TIMER REGISTERS  
Address  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
(1)  
(1)  
2007h  
Config. bits  
(1)  
BODEN  
CP1  
CP0  
PWRTE  
PSA  
WDTE  
PS2  
FOSC1  
PS1  
FOSC0  
PS0  
81h,181h  
OPTION_REG  
RBPU  
INTEDG  
T0CS  
T0SE  
Legend: Shaded cells are not used by the Watchdog Timer.  
Note 1: See Register 11-1 for operation of these bits.  
1999 Microchip Technology Inc.  
Preliminary  
DS30569A-page 101