PIC16F870/871
2.2.2.4
PIE1 REGISTER
Note: Bit PEIE (INTCON<6>) must be set to
The PIE1 Register contains the individual enable bits
for the peripheral interrupts.
enable any peripheral interrupt.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
PSPIE(1) ADIE
R/W-0
R/W-0
RCIE
R/W-0
TXIE
U-0
R/W-0
R/W-0
R/W-0
CCP1IE TMR2IE TMR1IE
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n= Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D converter interrupt
0= Disables the A/D converter interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
bit 3:
bit 2:
Unimplemented: Read as ‘0’
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
bit 1:
bit 0:
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: PSPIE is reserved on the PIC16F870; always maintain this bit clear.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 19