PIC16F870/871
TMR0 Register ................................................................... 13
TMR1CS bit ....................................................................... 51
TMR1H .............................................................................. 15
TMR1H Register ................................................................ 13
TMR1L ............................................................................... 15
TMR1L Register ................................................................. 13
TMR1ON bit ....................................................................... 51
TMR2 ................................................................................. 15
TMR2 Register ................................................................... 13
TMR2ON bit ....................................................................... 55
TOUTPS0 bit ..................................................................... 55
TOUTPS1 bit ..................................................................... 55
TOUTPS2 bit ..................................................................... 55
TOUTPS3 bit ..................................................................... 55
TRISA ................................................................................ 15
TRISA Register .................................................................. 14
TRISB ................................................................................ 15
TRISB Register .................................................................. 14
TRISC ................................................................................ 15
TRISC Register .................................................................. 14
TRISD ................................................................................ 15
TRISD Register .................................................................. 14
TRISE ................................................................................ 15
TRISE Register ............................................................ 14, 34
IBF Bit ........................................................................ 34
IBOV Bit ..................................................................... 34
OBF Bit ...................................................................... 34
PSPMODE Bit ................................................ 33, 34, 36
TXREG .............................................................................. 15
TXSTA ............................................................................... 15
TXSTA Register ................................................................. 63
BRGH Bit ................................................................... 63
CSRC Bit ................................................................... 63
SYNC Bit ................................................................... 63
TRMT Bit .................................................................... 63
TX9 Bit ....................................................................... 63
TX9D Bit .................................................................... 63
TXEN Bit .................................................................... 63
T
T1CKPS0 bit ......................................................................51
T1CKPS1 bit ......................................................................51
T1CON ...............................................................................15
T1CON Register ........................................................... 15, 51
T1OSCEN bit .....................................................................51
T1SYNC bit ........................................................................51
T2CKPS0 bit ......................................................................55
T2CKPS1 bit ......................................................................55
T2CON Register ........................................................... 15, 55
TAD .....................................................................................84
Timer0
Clock Source Edge Select (T0SE Bit) ........................17
Clock Source Select (T0CS Bit) .................................17
Overflow Enable (T0IE Bit) ........................................18
Overflow Flag (T0IF Bit) ..................................... 18, 100
Overflow Interrupt ....................................................100
RA4/T0CKI Pin, External Clock ...............................7, 8
Timer1 ................................................................................51
RC0/T1OSO/T1CKI Pin ...........................................7, 8
RC1/T1OSI/CCP2 Pin ..............................................7, 8
Timers
Timer0
External Clock ....................................................48
Interrupt ..............................................................47
Prescaler ............................................................48
Prescaler Block Diagram ...................................47
Section ...............................................................47
T0CKI .................................................................48
Timer1
Asynchronous Counter Mode ............................53
Capacitor Selection ............................................53
Operation in Timer Mode ...................................52
Oscillator ............................................................53
Prescaler ............................................................53
Resetting of Timer1 Registers ...........................53
Resetting Timer1 using a CCP Trigger Output ..53
Synchronized Counter Mode .............................52
T1CON ...............................................................51
TMR1H ...............................................................53
TMR1L ...............................................................53
Timer2
U
Universal Synchronous Asynchronous Receiver
Transmitter (USART)
Asynchronous Receiver
Block Diagram ....................................................55
Postscaler ..........................................................55
Prescaler ............................................................55
T2CON ...............................................................55
Timing Diagrams
Setting Up Reception ......................................... 71
Timing Diagram ................................................. 72
USART ............................................................................... 63
Asynchronous Mode .................................................. 67
Receive Block Diagram ..................................... 71
Asynchronous Receiver ............................................. 69
Asynchronous Reception ........................................... 70
Asynchronous Transmitter ......................................... 67
Baud Rate Generator (BRG) ..................................... 65
Baud Rate Formula ........................................... 65
Baud Rates, Asynchronous Mode (BRGH=0) ... 66
High Baud Rate Select (BRGH Bit) ................... 63
Sampling ............................................................ 65
Clock Source Select (CSRC Bit) ................................ 63
Continuous Receive Enable (CREN Bit) .................... 64
Framing Error (FERR Bit) .......................................... 64
Mode Select (SYNC Bit) ............................................ 63
Overrun Error (OERR Bit) .......................................... 64
RC6/TX/CK Pin ........................................................ 7, 8
RC7/RX/DT Pin ........................................................ 7, 8
RCSTA Register ........................................................ 64
Receive Block Diagram ............................................. 69
Receive Data, 9th bit (RX9D Bit) ............................... 64
A/D Conversion ........................................................134
Brown-out Reset ......................................................128
Capture/Compare/PWM ...........................................130
CLKOUT and I/O ......................................................127
Power-up Timer .......................................................128
Reset ........................................................................128
Start-up Timer ..........................................................128
Time-out Sequence on Power-up ........................97, 98
Timer0 ......................................................................129
Timer1 ......................................................................129
USART Asynchronous Master Transmission .............68
USART Asynchronous Reception ..............................69
USART Synchronous Receive .................................132
USART Synchronous Reception ................................75
USART Synchronous Transmission .................. 74, 132
USART, Asynchronous Reception .............................72
Wake-up from SLEEP via Interrupt ..........................103
Watchdog Timer .......................................................128
TMR0 .................................................................................15
DS30569A-page 148
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
