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PIC16F877-20/L 参数 Datasheet PDF下载

PIC16F877-20/L图片预览
型号: PIC16F877-20/L
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚8位CMOS闪存微控制器 [28/40-pin 8-Bit CMOS FLASH Microcontrollers]
分类和应用: 闪存微控制器
文件页数/大小: 200 页 / 3544 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F87X  
9.2.18 MULTI -MASTER COMMUNICATION, BUS  
COLLISION, AND BUS ARBITRATION  
If a START, Repeated Start, STOP or Acknowledge  
condition was in progress when the bus collision  
occurred, the condition is aborted, the SDA and SCL  
lines are deasserted, and the respective control bits in  
the SSPCON2 register are cleared. When the user  
services the bus collision interrupt service routine, and  
if the I2C bus is free, the user can resume communica-  
tion by asserting a START condition.  
Multi-Master mode support is achieved by bus arbitra-  
tion. When the master outputs address/data bits onto  
the SDA pin, arbitration takes place when the master  
outputs a ’1’ on SDA by letting SDA float high and  
another master asserts a ’0’. When the SCL pin floats  
high, data should be stable. If the expected data on  
SDA is a ’1’ and the data sampled on the SDA pin = ’0’,  
a bus collision has TACKEN place. The master will set  
the Bus Collision Interrupt Flag, BCLIF and reset the  
I2C port to its IDLE state. (Figure 9-19).  
The Master will continue to monitor the SDA and SCL  
pins, and if a STOP condition occurs, the SSPIF bit will  
be set.  
A write to the SSPBUF will start the transmission of  
data at the first data bit, regardless of where the trans-  
mitter left off when the bus collision occurred.  
If a transmit was in progress when the bus collision  
occurred, the transmission is halted, the BF flag is  
cleared, the SDA and SCL lines are deasserted, and  
the SSPBUF can be written to. When the user services  
the bus collision interrupt service routine, and if the I2C  
bus is free, the user can resume communication by  
asserting a START condition.  
In multi-master mode, the interrupt generation on the  
detection of start and stop conditions allows the deter-  
mination of when the bus is free. Control of the I2C bus  
can be TACKEN when the P bit is set in the SSPSTAT  
register, or the bus is idle and the S and P bits are  
cleared.  
FIGURE 9-19: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE  
Sample SDA. While SCL is high,  
data doesn’t match what is driven  
by the master.  
SDA line pulled low  
by another source  
Data changes  
while SCL = 0  
Bus collision has occurred.  
SDA released  
by master  
SDA  
SCL  
Set bus collision  
interrupt.  
BCLIF  
DS30292A-page 88  
1999 Microchip Technology Inc.  
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