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PIC16F877-20/L 参数 Datasheet PDF下载

PIC16F877-20/L图片预览
型号: PIC16F877-20/L
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚8位CMOS闪存微控制器 [28/40-pin 8-Bit CMOS FLASH Microcontrollers]
分类和应用: 闪存微控制器
文件页数/大小: 200 页 / 3544 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F87X  
9.2.5  
MASTER MODE  
In master mode, the SCL and SDA lines are manipu-  
lated by the MSSP hardware.  
Master mode of operation is supported by interrupt  
generation on the detection of the START and STOP  
conditions. The STOP (P) and START (S) bits are  
cleared from a reset or when the MSSP module is dis-  
abled. Control of the I2C bus may be TACKEN when the  
P bit is set, or the bus is idle with both the S and P bits  
clear.  
The following events will cause the SSP Interrupt Flag  
bit, SSPIF, to be set (SSP Interrupt if enabled):  
• START condition  
• STOP condition  
• Data transfer byte transmitted/received  
• Acknowledge transmit  
• Repeated Start  
2
FIGURE 9-9: SSP BLOCK DIAGRAM (I C MASTER MODE)  
Internal  
Data Bus  
SSPM3:SSPM0,  
SSPADD<6:0>  
Read  
Write  
SSPBUF  
SSPSR  
Baud  
Rate  
Generator  
SDA  
Shift  
Clock  
SDA in  
MSb  
LSb  
Start bit, Stop bit,  
Acknowledge  
Generate  
SCL  
Start bit detect,  
Stop bit detect  
Write collision detect  
Clock Arbitration  
State counter for  
end of XMIT/RCV  
SCL in  
Bus Collision  
Set/Reset, S, P, WCOL (SSPSTAT)  
Set SSPIF, BCLIF  
Reset ACKSTAT, PEN (SSPCON2)  
DS30292A-page 76  
1999 Microchip Technology Inc.