PIC16F87X
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[label] BTFSS f,b
Syntax:
[label] CLRF
0 ≤ f ≤ 127
f
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected:
Description:
Z
Description:
If bit ’b’ in register ’f’ is ’0’, the next
The contents of register ’f’ are
cleared and the Z bit is set.
instruction is executed.
If bit ’b’ is ’1’, then the next instruc-
tion is discarded and a NOPis exe-
cuted instead making this a 2TCY
instruction.
CLRW
Clear W
Syntax:
[ label ] CLRW
None
BTFSC
Bit Test, Skip if Clear
Operands:
Operation:
Syntax:
[label] BTFSC f,b
00h → (W)
1 → Z
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Status Affected:
Description:
Z
Operation:
skip if (f<b>) = 0
W register is cleared. Zero bit (Z)
is set.
Status Affected: None
Description:
If bit ’b’ in register ’f’ is ’1’, the next
instruction is executed.
If bit ’b’, in register ’f’, is ’0’, the
next instruction is discarded, and
a NOPis executed instead, making
this a 2TCY instruction.
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
CALL
Call Subroutine
Operands:
Operation:
Syntax:
[ label ] CALL k
00h → WDT
0 → WDT prescaler,
1 → TO
Operands:
Operation:
0 ≤ k ≤ 2047
(PC)+ 1→ TOS,
k → PC<10:0>,
1 → PD
(PCLATH<4:3>) → PC<12:11>
Status Affected: TO, PD
Status Affected: None
Description: CLRWDTinstruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
Description:
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALLis
a two cycle instruction.
DS30292B-page 140
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
