PIC16F87X
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
12.10 Interrupts
The PIC16F87X family has up to 14 sources of inter-
rupt. The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has indi-
vidual and global interrupt enable bits.
The peripheral interrupt flags are contained in the spe-
cial function registers, PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
Note: Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set regardless of the status of
their corresponding mask bit or the GIE bit
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 12-9: INTERRUPT LOGIC
EEIF
EEIE
PSPIF
PSPIE
Wake-up (If in SLEEP mode)
ADIF
ADIE
T0IF
T0IE
RCIF
RCIE
INTF
INTE
Interrupt to CPU
TXIF
TXIE
RBIF
RBIE
SSPIF
SSPIE
PEIE
GIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
BCLIF
BCLIE
The following table shows which devices have which interrupts.
Device
T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF EEIF BCLIF CCP2IF
PIC16F876/873 Yes Yes Yes
PIC16F877/874 Yes Yes Yes
-
Yes
Yes
Yes Yes
Yes Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1999 Microchip Technology Inc.
DS30292B-page 131
MICROCHIP [ MICROCHIP ]
