PIC16F7X7
4.7.2
SEC_RUN MODE
Note 1: The T1OSCEN bit must be enabled and it
is the user’s responsibility to ensure
T1OSC is stable before clock switching to
the T1OSC input clock can occur.
The core and peripherals can be configured to be
clocked by T1OSC using a 32.768 kHz crystal. The
crystal must be connected to the T1OSO and T1OSI
pins. This is the same configuration as the low-power
timer circuit (see Section 7.6 “Timer1 Oscillator”).
When SCS bits are configured to run from T1OSC, a
clock transition is generated. It will clear the OSTS bit,
switch the system clock from either the primary system
clock or INTRC, depending on the value of SCS<1:0>
and FOSC<2:0>, to the external low-power Timer1
oscillator input (T1OSC) and shut-down the primary
system clock to conserve power.
2: When T1OSCEN = 0, the following
possible effects result.
Original Modified
SCS<1:0> SCS<1:0>
Final
SCS<1:0>
00
00
10
10
01
11
11
01
00– no change
10– INTRC
10– no change
After a clock switch has been executed, the internal Q
clocks are held in the Q1 state until eight falling edge
clocks are counted on the T1OSC. After the eight clock
periods have transpired, the clock input to the Q clocks
is released and operation resumes (see Figure 4-8). In
addition, T1RUN (in T1CON) is set to indicate that
T1OSC is being used as the system clock.
00– Oscillator
defined by
FOSC<2:0>
A clock switching event will occur if the
final state of the SCS bits is different from
the original.
FIGURE 4-8:
TIMING DIAGRAM FOR SWITCHING TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q1 Q2
Q3
Q4
Q1
Q2
Q3
Q4 Q1
(1)
TT1P
T1OSI
OSC1
(3)
TSCS
(2)
TOSC
System
Clock
(4)
TDLY
SCS<1:0>
Program
Counter
PC
PC + 1
PC + 2
PC + 3
Note 1: TT1P = 30.52 µs.
2: TOSC = 50 ns minimum.
3: TSCS = 8 TT1P
4: TDLY = 1 TT1P.
DS30498C-page 42
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
