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PIC16F767-I/SP 参数 Datasheet PDF下载

PIC16F767-I/SP图片预览
型号: PIC16F767-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚, 8位CMOS闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 276 页 / 4898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F7X7  
Even if the flag bits were checked before executing a  
SLEEP instruction, it may be possible for flag bits to  
become set before the SLEEPinstruction completes. To  
determine whether a SLEEPinstruction executed, test  
the PD bit. If the PD bit is set, the SLEEP instruction  
was executed as a NOP.  
15.18.2 WAKE-UP USING INTERRUPTS  
When global interrupts are disabled (GIE cleared) and  
any interrupt source has both its interrupt enable bit  
and interrupt flag bit set, one of the following will occur:  
• If the interrupt occurs before the execution of a  
SLEEPinstruction, the SLEEPinstruction will  
complete as a NOP. Therefore, the WDT and WDT  
prescaler and postscaler (if enabled) will not be  
cleared, the TO bit will not be set and the PD bit  
will not be cleared.  
To ensure that the WDT is cleared, a CLRWDTinstruction  
should be executed before a SLEEPinstruction.  
• If the interrupt occurs during or after the  
execution of a SLEEPinstruction, the device will  
immediately wake-up from Sleep. The SLEEP  
instruction will be completely executed before the  
wake-up. Therefore, the WDT and WDT prescaler  
and postscaler (if enabled) will be cleared, the TO  
bit will be set and the PD bit will be cleared.  
FIGURE 15-16:  
WAKE-UP FROM SLEEP THROUGH INTERRUPT  
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1  
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4  
OSC1  
(2)  
CLKO(4)  
TOST  
INT pin  
INTF Flag  
(INTCON<1>)  
Interrupt Latency  
(Note 2)  
GIE bit  
(INTCON<7>)  
Processor in  
Sleep  
INSTRUCTION FLOW  
PC  
PC  
PC + 1  
PC + 2  
PC + 2  
PC + 2  
0004h  
0005h  
Instruction  
Fetched  
Inst(0004h)  
Inst(PC + 1)  
Inst(PC + 2)  
Inst(0005h)  
Inst(PC) = Sleep  
Instruction  
Executed  
Dummy Cycle  
Dummy Cycle  
Sleep  
Inst(PC + 1)  
Inst(PC – 1)  
Inst(0004h)  
Note 1: XT, HS or LP Oscillator mode assumed.  
2: TOST = 1024 TOSC (drawing not to scale). This delay will not be there for RC Oscillator mode.  
3: GIE = 1assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.  
4: CLKO is not available in these oscillator modes but shown here for timing reference.  
2004 Microchip Technology Inc.  
DS30498C-page 191  
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