PIC16F7X7
Some registers are not affected in any Reset condition.
Their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR Reset during Sleep and Brown-
out Reset (BOR). They are not affected by a WDT
wake-up which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared
differently in different Reset situations, as indicated in
Table 15-3. These bits are used in software to
determine the nature of the Reset. Upon a POR, BOR
or wake-up from Sleep, the CPU requires approxi-
mately 5-10 µs to become ready for code execution.
This delay runs in parallel with any other timers. See
Table 15-4 for a full description of Reset states of all
registers.
15.2 Reset
The PIC16F7X7 differentiates between various kinds of
Reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during Sleep
• WDT Reset during normal operation
• WDT Wake-up during Sleep
• Brown-out Reset (BOR)
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 15-1.
FIGURE 15-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/VPP/RE3 pin
Sleep
WDT
WDT
Module
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Detect
BOREN
BORSEN
S
OST/PWRT
OST
10-bit Ripple Counter
Chip_Reset
R
Q
OSC1/
CLKI pin
PWRT
11-bit Ripple Counter
INTRC(1)
Enable PWRT
Enable OST
Note 1: This is the 32 kHz INTRC oscillator. See Section 4.0 “Oscillator Configurations” for more information.
DS30498C-page 172
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
