PIC16F7X7
FIGURE 1-2:
PIC16F747 AND PIC16F777 BLOCK DIAGRAM
PORTA
13
Standard
Flash
Program
Memory
4K/8K x 14
Program Counter
Data Bus
8
RA0/AN0
RA1/AN1
RA2/AN2/V
REF
-/CV
REF
RA3/AN3/V
REF
+
RA4/T0CKI/C1OUT
RA5/AN4/LVDIN/
SS/C2OUT
OSC2/CLKO/RA6
OSC1/CLKI/RA7
PORTB
RB0/INT/AN12
RB1/AN10
RB2/AN8
RB3/CCP2
(1)
/AN9
RB4/AN11
RB5/AN13/CCP3
RB7/PGD:RB6/PGC
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
PORTD
WREG
RD7/PSP7:RD0/PSP0
Parallel Slave Port
8-Level Stack
(13-bit)
RAM
File
Registers
368 x 8
RAM Addr
(1)
9
Program
Bus
14
Instruction Register
Direct Addr
7
Addr MUX
8
Indirect
Addr
FSR reg
Status reg
8
3
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
8
MUX
ALU
V
DD
, V
SS
PORTE
RE0/RD/AN5
RE1/WR/AN6
Timer0
Timer1
Timer2
10-bit A/D
RE2/CS/AN7
MCLR/V
PP
/RE3
Comparators
CCP1, 2, 3
MSSP
Addressable
USART
BOR/LVD
Note 1:
Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
2004 Microchip Technology Inc.
DS30498C-page 7