欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC16C57C-04I/SO 参数 Datasheet PDF下载

PIC16C57C-04I/SO图片预览
型号: PIC16C57C-04I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 基于ROM的8位CMOS微控制器系列 [ROM-Based 8-Bit CMOS Microcontroller Series]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC可编程只读存储器时钟
文件页数/大小: 84 页 / 641 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第37页浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第38页浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第39页浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第40页浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第42页浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第43页浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第44页浏览型号PIC16C57C-04I/SO的Datasheet PDF文件第45页  
PIC16CR54C  
CALL  
Subroutine Call  
[ label ] CALL  
0 k 255  
CLRW  
Clear W  
Syntax:  
k
Syntax:  
[ label ] CLRW  
None  
Operands:  
Operation:  
Operands:  
Operation:  
(PC) + 1Top of Stack;  
k PC<7:0>;  
00h (W);  
1 Z  
(STATUS<6:5>) PC<10:9>;  
0 PC<8>  
Status Affected:  
Encoding:  
Z
0000  
0100  
0000  
Status Affected: None  
The W register is cleared. Zero bit (Z)  
is set.  
Description:  
1001  
kkkk  
kkkk  
Encoding:  
Subroutine call. First, return address  
(PC+1) is pushed onto the stack. The  
eight bit immediate address is loaded  
into PC bits <7:0>. The upper bits  
PC<10:9> are loaded from STA-  
TUS<6:5>, PC<8> is cleared. CALLis  
a two cycle instruction.  
Description:  
Words:  
1
Cycles:  
Example:  
1
CLRW  
Before Instruction  
0x5A  
W
=
After Instruction  
Words:  
1
2
W
=
0x00  
Cycles:  
Example:  
Z
=
1
HERE  
CALL  
THERE  
Before Instruction  
PC address (HERE)  
CLRWDT  
Clear Watchdog Timer  
[ label ] CLRWDT  
None  
=
Syntax:  
After Instruction  
PC address (THERE)  
TOS =  
=
Operands:  
Operation:  
address (HERE + 1)  
00h WDT;  
0 WDT prescaler (if assigned);  
1 TO;  
1 PD  
CLRF  
Clear f  
Syntax:  
[ label ] CLRF  
f
Status Affected: TO, PD  
Operands:  
Operation:  
0 f 31  
0000  
0000  
0100  
Encoding:  
00h (f);  
1 Z  
The CLRWDTinstruction resets the  
WDT. It also resets the prescaler, if the  
prescaler is assigned to the WDT and  
not Timer0. Status bits TO and PD are  
set.  
Description:  
Status Affected:  
Encoding:  
Z
0000  
011f  
ffff  
The contents of register 'f' are cleared  
and the Z bit is set.  
Description:  
Words:  
1
Cycles:  
Example:  
1
Words:  
1
1
CLRWDT  
Cycles:  
Example:  
Before Instruction  
CLRF  
FLAG_REG  
WDT counter  
=
=
?
Before Instruction  
FLAG_REG  
After Instruction  
WDT counter  
=
0x5A  
0x00  
After Instruction  
WDT prescale =  
0
1
1
FLAG_REG  
Z
=
=
0x00  
1
TO  
PD  
=
=
1998 Microchip Technology Inc.  
Preliminary  
DS40191A-page 41  
 复制成功!