PIC16CR54C
outputs are latched and remain unchanged until the
output latch is rewritten. To use a port pin as output,
the corresponding direction control bit (in TRISA,
TRISB) must be cleared (= 0). For use as an input, the
corresponding TRIS bit must be set. Any I/O pin can
be programmed individually as input or output.
5.0
I/O PORTS
As with any other register, the I/O registers can be
written and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance) since the I/O control registers (TRISA,
TRISB, TRISC) are all set.
FIGURE 5-1: EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
5.1
PORTA
D
Q
Q
PORTA is a 4-bit I/O register. Only the low order 4 bits
are used (RA3:RA0). Bits 7-4 are unimplemented and
read as '0's.
Data
Latch
VDD
P
WR
Port
CK
5.2
PORTB
N
I/O
pin(1)
PORTB is an 8-bit I/O register (PORTB<7:0>).
W
Reg
D
Q
Q
5.3
TRIS Registers
TRIS
Latch
VSS
The output driver control registers are loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer.
TRIS ‘f’
CK
Reset
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
5.4
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All ports may be used for both input and
output operation. For input operations these ports are
non-latching. Any input must be present until read by
an input instruction (e.g., MOVF PORTB, W). The
TABLE 5-1:
SUMMARY OF PORT REGISTERS
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset
Address
Name
TRIS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N/A
05h
06h
I/O control registers (TRISA, TRISB)
1111 1111 1111 1111
---- xxxx ---- uuuu
xxxx xxxx uuuu uuuu
PORTA
PORTB
—
—
—
—
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0
RB7
RB6
RB5
RB4
Legend: Shaded boxes = unimplemented, read as ‘0’,
–= unimplemented, read as '0', x= unknown, u= unchanged
1998 Microchip Technology Inc.
Preliminary
DS40191A-page 19
MICROCHIP [ MICROCHIP ]
