PIC16F7X7
FIGURE 5-3:
BLOCK DIAGRAM OF RA2/AN2/VREF-/CVREF PIN
Data
Bus
Q
D
VDD
WR
PORTA
CK
Q
P
Data Latch
D
Q
RA2/AN2/VREF-/
CVREF pin
N
WR
TRISA
CK
Q
VSS
TRIS Latch
Analog
Input Mode
TTL
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
To Comparator
To A/D Module VREF-
To A/D Module Channel Input
CVROE
CVREF
FIGURE 5-4:
BLOCK DIAGRAM OF RA4/T0CKI/C1OUT PIN
Data
Bus
Comparator Mode = 011, 101, 001
D
Q
Comparator 1 Output
WR
PORTA
1
CK
Q
0
Data Latch
D
Q
RA4/T0CKI/
C1OUT pin
N
WR
TRISA
CK
Q
VSS
Analog
Input Mode
TRIS Latch
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
TMR0 Clock Input
2004 Microchip Technology Inc.
DS30498C-page 51