PIC16F7X7
REGISTER 12-2: ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh)
R/W-0
ADFM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCS2
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1 PCFG0
bit 0
bit 7
bit 7
bit 6
bit 5
bit 4
bit 3-0
ADFM: A/D Result Format Select bit
1= Right justified. Six Most Significant bits of ADRESH are read as ‘0’.
0= Left justified. Six Least Significant bits of ADRESL are read as ‘0’.
ADCS2: A/D Clock Divide by 2 Select bit
1= A/D clock source is divided by two when system clock is used
0= Disabled
VCFG1: Voltage Reference Configuration bit 1
0= VREF- is connected to VSS
1= VREF- is connected to external VREF- (RA2)
VCFG0: Voltage Reference Configuration bit 0
0= VREF+ is connected to VDD
1= VREF+ is connected to external VREF+ (RA3)
PCFG<3:0>: A/D Port Configuration bits
AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Legend:
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
A = Analog input, D = Digital I/O
Note:
AN5 through AN7 are only available on the 40-pin product variant (PIC16F747 and
PIC16F777).
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc.
DS30498C-page 153
MICROCHIP [ MICROCHIP ]
