PIC16F7X7
10.4.4
CLOCK STRETCHING
10.4.4.3
Clock Stretching for 7-bit Slave
Transmit Mode
Both 7-bit and 10-bit Slave modes implement
automatic clock stretching during a transmit sequence.
7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
ninth clock, if the BF bit is clear. This occurs
regardless of the state of the SEN bit.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 10-9).
10.4.4.1
Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock, at the end of the ACK sequence if the BF bit
is set, the CKP bit in the SSPCON register is auto-
matically cleared, forcing the SCL output to be held low.
The CKP being cleared to ‘0’ will assert the SCL line
low. The CKP bit must be set in the user’s ISR before
reception is allowed to continue. By holding the SCL
line low, the user has time to service the ISR and read
the contents of the SSPBUF before the master device
can initiate another receive sequence. This will prevent
buffer overruns from occurring (see Figure 10-13).
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
10.4.4.4
Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is
controlled during the first two address sequences by
the state of the UA bit, just as it is in 10-bit Slave
Receive mode. The first two addresses are followed
by a third address sequence, which contains the high-
order bits of the 10-bit address and the R/W bit set to
‘1’. After the third address sequence is performed, the
UA bit is not set, the module is now configured in
Transmit mode and clock stretching is controlled by
the BF flag as in 7-bit Slave Transmit mode (see
Figure 10-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
10.4.4.2
Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address, with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
DS30498C-page 112
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
