PIC16F87X
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
Value on:
Addres
all other
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
s
resets
(2)
Bank 2
100h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000
0000 0000
101h
TMR0
PCL
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
102h(4)
103h(4)
Program Counter's (PC) Least Significant Byte
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
104h(4)
105h
106h
107h
108h
109h
FSR
—
Indirect data memory address pointer
Unimplemented
xxxx xxxx uuuu uuuu
—
—
PORTB
—
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
10Ah(1,4)
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE RBIE T0IF INTF RBIF
---0 0000 ---0 0000
0000 000x 0000 000u
10Bh(4)
10Ch
10Dh
10Eh
10Fh
INTCON
GIE
PEIE
T0IE
EEDATA
EEADR
EEPROM data register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
EEPROM address register
EEDATH
EEADRH
—
—
—
—
EEPROM data register high byte
EEPROM address register high byte
—
Bank 3
180h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
OPTION_R
EG
181h
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
182h(4)
183h(4)
PCL
Program Counter's (PC) Least Significant Byte
IRP RP1 RP0 TO
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
STATUS
PD
Z
DC
C
184h(4)
185h
186h
187h
188h
189h
FSR
—
Indirect data memory address pointer
Unimplemented
—
—
TRISB
—
PORTB Data Direction Register
Unimplemented
1111 1111 1111 1111
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
18Ah(1,4)
Write Buffer for the upper 5 bits of the Program Counter
PCLATH
—
—
—
---0 0000 ---0 0000
18Bh(4)
18Ch
18Dh
18Eh
18Fh
INTCON
EECON1
EECON2
—
GIE
PEIE
—
T0IE
—
INTE
—
RBIE
T0IF
INTF
WR
RBIF
RD
0000 000x 0000 000u
x--- x000 x--- u000
---- ---- ---- ----
0000 0000 0000 0000
0000 0000 0000 0000
EEPGD
WRERR
WREN
EEPROM control register2 (not a physical register)
Reserved maintain clear
—
Reserved maintain clear
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
1999 Microchip Technology Inc.
DS30292B-page 17
MICROCHIP [ MICROCHIP ]
