PIC16F7X
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled to support Firmware
Master mode
2
9.3
SSP I C Operation
The SSP module in I2C mode, fully implements all slave
functions, except general call support, and provides
interrupts on START and STOP bits in hardware to facil-
itate firmware implementations of the master functions.
The SSP module implements the standard mode speci-
fications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
• I2C Slave mode (10-bit address), with START and
STOP bit interrupts enabled to support Firmware
Master mode
• I2C START and STOP bit interrupts enabled to
support Firmware Master mode, Slave is IDLE
The SSP module functions are enabled by setting SSP
enable bit SSPEN (SSPCON<5>).
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits. Pull-up resistors must be
provided externally to the SCL and SDA pins for proper
operation of the I2C module.
Additional information on SSP I2C operation can be
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023A).
FIGURE 9-5:
SSP BLOCK DIAGRAM
(I2C MODE)
Internal
Data Bus
Read
Write
SSPBUF reg
RC3/SCK/SCL
9.3.1
SLAVE MODE
Shift
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
Clock
SSPSR reg
RC4/
SDI/
SDA
MSb
LSb
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
Addr Match
Match Detect
SSPADD reg
There are certain conditions that will cause the SSP
module not to give this ACK pulse. They include (either
or both):
Set, RESET
S, P bits
(SSPSTAT reg)
START and
STOP bit Detect
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The SSP module has five registers for I2C operation.
These are the:
b) The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
• SSP Control Register (SSPCON)
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 9-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF reg-
ister, while bit SSPOV is cleared through software.
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly accessible
• SSP Address Register (SSPADD)
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirements of the
SSP module, are shown in timing parameter #100 and
parameter #101.
2002 Microchip Technology Inc.
DS30325B-page 65
MICROCHIP [ MICROCHIP ]
