PIC16F7X
however, these lines must be used to set a temporary
value. The final 1:1 value is then set in lines 10 and 11
(highlighted). (Line numbers are included in the exam-
ple for illustrative purposes only, and are not part of the
actual code.)
5.3
Prescaler
There is only one prescaler available on the microcon-
troller; it is shared exclusively between the Timer0
module and the Watchdog Timer. The usage of the
prescaler is also mutually exclusive: that is, a prescaler
assignment for the Timer0 module means that there is
no prescaler for the Watchdog Timer, and vice versa.
This prescaler is not readable or writable (see
Figure 5-1).
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF1, MOVWF1,
BSF1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Examples of code for assigning the prescaler assign-
ment are shown in Example 5-1 and Example 5-2.
Note that when the prescaler is being assigned to the
WDT with ratios other than 1:1, lines 2 and 3 (high-
lighted) are optional. If a prescale ratio of 1:1 is to used,
Note: Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the prescaler
count but will not change the prescaler
assignment.
EXAMPLE 5-1:
CHANGING THE PRESCALER ASSIGNMENT FROM TIMER0 TO WDT
1) BSF
STATUS, RP0
; Bank1
2) MOVLW
3) MOVWF
4) BCF
5) CLRF
6) BSF
7) MOVLW
8) MOVWF
9) CLRWDT
10) MOVLW
11) MOVWF
12) BCF
b’xx0x0xxx’
; Select clock source and prescale value of
; other than 1:1
; Bank0
; Clear TMR0 and prescaler
; Bank1
; Select WDT, do not change prescale value
OPTION_REG
STATUS, RP0
TMR0
STATUS, RP1
b’xxxx1xxx’
OPTION_REG
; Clears WDT and prescaler
; Select new prescale value and WDT
b’xxxx1xxx’
OPTION_REG
STATUS, RP0
; Bank0
EXAMPLE 5-2:
CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0
CLRWDT
BSF
MOVLW
MOVWF
BCF
; Clear WDT and prescaler
; Bank1
; Select TMR0, new prescale
; value and clock source
; Bank0
STATUS, RP0
b’xxxx0xxx’
OPTION_REG
STATUS, RP0
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h,101h
TMR0
Timer0 Module Register
GIE PEIE TMR0IE INTE
OPTION_REG RBPU INTEDG T0CS T0SE
xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh
INTCON
RBIE TMR0IF INTF
PSA PS2 PS1
RBIF 0000 000x 0000 000u
PS0 1111 1111 1111 1111
81h,181h
Legend: x= unknown, u= unchanged, -= unimplemented locations read as ’0’. Shaded cells are not used by Timer0.
2002 Microchip Technology Inc.
DS30325B-page 45
MICROCHIP [ MICROCHIP ]
