PIC16C71X
WDT Reset, on MCLR reset during SLEEP, and Brown-
out Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation.The TO and PD bits are set or cleared differ-
ently in different reset situations as indicated in Table 8-
7, Table 8-8 and Table 8-9. These bits are used in soft-
ware to determine the nature of the reset. See Table 8-
10 and Table 8-11 for a full description of reset states
of all registers.
8.3
Reset
Applicable Devices 710 71 711 715
The PIC16CXX differentiates between various kinds of
reset:
• Power-on Reset (POR)
• MCLR reset during normal operation
• MCLR reset during SLEEP
A simplified block diagram of the on-chip reset circuit is
shown in Figure 8-9.
• WDT Reset (normal operation)
• Brown-out Reset (BOR) (PIC16C710/711/715)
• Parity Error Reset (PIC16C715)
The PIC16C710/711/715 have a MCLR noise filter in
the MCLR reset path. The filter will detect and ignore
small pulses.
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 8-9: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/VPP Pin
MPEEN
Program
Memory
Parity
(3)
WDT
Module
SLEEP
WDT Time-out
Power-on Reset
VDD rise
detect
VDD
Brown-out
(2)
S
R
Reset
BODEN
OST/PWRT
OST
10-bit Ripple-counter
Chip_Reset
Q
OSC1/
CLKIN
Pin
PWRT
10-bit Ripple-counter
(1)
On-chip
RC OSC
Enable PWRT
Enable OST
See Table 8-6 for time-out situations.
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: Brown-out Reset is implemented on the PIC16C710/711/715.
3: Parity Error Reset is implemented on the PIC16C715.
DS30272A-page 52
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
