PIC16C71X
7.1
A/D Acquisition Requirements
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 7-5. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD),
Figure 7-5. The source impedance affects the offset
voltage at the analog input (due to pin leakage current).
The maximum recommended impedance for ana-
log sources is 10 kΩ. After the analog input channel is
selected (changed) this acquisition must be done
before the conversion can be started.
Note 2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
Note 3: The maximum recommended impedance
for analog sources is 10 kΩ. This is
required to meet the pin leakage specifi-
cation.
Note 4: After a conversion has completed, a
2.0TAD delay must complete before acqui-
sition can begin again. During this time the
holding capacitor is not connected to the
selected A/D input channel.
To calculate the minimum acquisition time, Equation 7-
1 may be used.This equation calculates the acquisition
time to within 1/2 LSb error is used (512 steps for the
A/D). The 1/2 LSb error is the maximum error allowed
for the A/D to meet its specified accuracy.
EXAMPLE 7-1: CALCULATING THE
MINIMUM REQUIRED
AQUISITION TIME
TACQ = Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
EQUATION 7-1:
A/D MINIMUM CHARGING
TIME
(-TCAP/CHOLD(RIC + RSS + RS))
TACQ = 5 µs + TCAP + [(Temp - 25°C)(0.05 µs/°C)]
TCAP = -CHOLD (RIC + RSS + RS) ln(1/511)
-51.2 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0020)
-51.2 pF (18 kΩ) ln(0.0020)
VHOLD = (VREF - (VREF/512)) • (1 - e
)
Given: VHOLD = (VREF/512), for 1/2 LSb resolution
The above equation reduces to:
TCAP = -(51.2 pF)(1 kΩ + RSS + RS) ln(1/511)
Example 7-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following system assumptions.
-0.921 µs (-6.2364)
5.747 µs
TACQ = 5 µs + 5.747 µs + [(50°C - 25°C)(0.05 µs/°C)]
10.747 µs + 1.25 µs
CHOLD = 51.2 pF
Rs = 10 kΩ
11.997 µs
1/2 LSb error
VDD = 5V → Rss = 7 kΩ
Temp (application system max.) = 50°C
VHOLD = 0 @ t = 0
FIGURE 7-5: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
Rs
CHOLD
= DAC capacitance
= 51.2 pF
CPIN
5 pF
VA
I leakage
± 500 nA
VT = 0.6V
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
I leakage = leakage current at the pin due to
various junctions
VDD 4V
3V
2V
RIC
SS
= interconnect resistance
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
5 6 7 8 9 10 11
Sampling Switch
( kΩ )
DS30272A-page 40
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
