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PIC16C71-04/SO 参数 Datasheet PDF下载

PIC16C71-04/SO图片预览
型号: PIC16C71-04/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 8位CMOS微控制器与A / D转换器 [8-Bit CMOS Microcontrollers with A/D Converter]
分类和应用: 转换器微控制器
文件页数/大小: 176 页 / 1596 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16C71X  
bit T0SE selects the rising edge. Restrictions on the  
external clock input are discussed in detail in  
Section 6.2.  
6.0  
TIMER0 MODULE  
Applicable Devices 710 71 711 715  
The Timer0 module timer/counter has the following fea-  
tures:  
The prescaler is mutually exclusively shared between  
the Timer0 module and the Watchdog Timer. The pres-  
caler assignment is controlled in software by control bit  
PSA (OPTION<3>). Clearing bit PSA will assign the  
prescaler to the Timer0 module. The prescaler is not  
readable or writable.When the prescaler is assigned to  
the Timer0 module, prescale values of 1:2, 1:4, ...,  
1:256 are selectable. Section 6.3 details the operation  
of the prescaler.  
• 8-bit timer/counter  
• Readable and writable  
• 8-bit software programmable prescaler  
• Internal or external clock select  
• Interrupt on overflow from FFh to 00h  
• Edge select for external clock  
Figure 6-1 is a simplified block diagram of the Timer0  
module.  
6.1  
Timer0 Interrupt  
The TMR0 interrupt is generated when the TMR0 reg-  
ister overflows from FFh to 00h. This overflow sets bit  
T0IF (INTCON<2>). The interrupt can be masked by  
clearing bit T0IE (INTCON<5>). Bit T0IF must be  
cleared in software by the Timer0 module interrupt ser-  
vice routine before re-enabling this interrupt. The  
TMR0 interrupt cannot awaken the processor from  
SLEEP since the timer is shut off during SLEEP. See  
Figure 6-4 for Timer0 interrupt timing.  
Timer mode is selected by clearing bit T0CS  
(OPTION<5>). In timer mode, the Timer0 module will  
increment every instruction cycle (without prescaler). If  
the TMR0 register is written, the increment is inhibited  
for the following two instruction cycles (Figure 6-2 and  
Figure 6-3). The user can work around this by writing  
an adjusted value to the TMR0 register.  
Counter mode is selected by setting bit T0CS  
(OPTION<5>). In counter mode, Timer0 will increment  
either on every rising or falling edge of pin RA4/T0CKI.  
The incrementing edge is determined by the Timer0  
Source Edge Select bit T0SE (OPTION<4>). Clearing  
FIGURE 6-1: TIMER0 BLOCK DIAGRAM  
Data bus  
FOSC/4  
0
1
PSout  
8
1
0
Sync with  
Internal  
clocks  
TMR0  
Programmable  
Prescaler  
RA4/T0CKI  
pin  
PSout  
(2 cycle delay)  
T0SE  
3
Set interrupt  
flag bit T0IF  
on overflow  
PS2, PS1, PS0  
PSA  
T0CS  
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).  
2: The prescaler is shared with Watchdog Timer (refer to Figure 6-6 for detailed block diagram).  
FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE  
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4  
PC  
(Program  
Counter)  
PC-1  
PC  
PC+1  
PC+2  
PC+3  
PC+4  
PC+5  
PC+6  
Instruction  
Fetch  
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W  
MOVWF TMR0  
T0  
T0+1  
T0+2  
NT0  
NT0  
NT0  
NT0+1  
NT0+2  
TMR0  
Instruction  
Executed  
Read TMR0  
reads NT0 + 1  
Read TMR0  
reads NT0  
Read TMR0  
reads NT0  
Read TMR0  
reads NT0  
Read TMR0  
reads NT0 + 2  
Write TMR0  
executed  
1997 Microchip Technology Inc.  
DS30272A-page 31  
 
 
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