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PIC16C71-04/SO 参数 Datasheet PDF下载

PIC16C71-04/SO图片预览
型号: PIC16C71-04/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 8位CMOS微控制器与A / D转换器 [8-Bit CMOS Microcontrollers with A/D Converter]
分类和应用: 转换器微控制器
文件页数/大小: 176 页 / 1596 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16C71X  
Example 4-1 shows the calling of a subroutine in  
page 1 of the program memory.This example assumes  
that PCLATH is saved and restored by the interrupt ser-  
vice routine (if interrupts are used).  
4.5  
Indirect Addressing, INDF and FSR  
Registers  
The INDF register is not a physical register. Addressing  
the INDF register will cause indirect addressing.  
Indirect addressing is possible by using the INDF reg-  
ister. Any instruction using the INDF register actually  
accesses the register pointed to by the File Select Reg-  
ister, FSR. Reading the INDF register itself indirectly  
(FSR = '0') will read 00h. Writing to the INDF register  
indirectly results in a no-operation (although status bits  
may be affected). An effective 9-bit address is obtained  
by concatenating the 8-bit FSR register and the IRP bit  
(STATUS<7>), as shown in Figure 4-15. However, IRP  
is not used in the PIC16C71X devices.  
EXAMPLE 4-1: CALL OF A SUBROUTINE IN  
PAGE 1 FROM PAGE 0  
ORG 0x500  
BSF  
BCF  
PCLATH,3 ;Select page 1 (800h-FFFh)  
PCLATH,4 ;Only on >4K devices  
CALL  
SUB1_P1  
;Call subroutine in  
;page 1 (800h-FFFh)  
:
:
:
ORG 0x900  
SUB1_P1:  
;called subroutine  
;page 1 (800h-FFFh)  
A simple program to clear RAM locations 20h-2Fh  
using indirect addressing is shown in Example 4-2.  
:
:
RETURN  
;return to Call subroutine  
;in page 0 (000h-7FFh)  
EXAMPLE 4-2: INDIRECT ADDRESSING  
movlw 0x20  
movwf FSR  
;initialize pointer  
;to RAM  
NEXT  
clrf  
incf  
INDF  
;clear INDF register  
FSR,F ;inc pointer  
btfss FSR,4 ;all done?  
goto  
NEXT  
;no clear next  
CONTINUE  
:
;yes continue  
FIGURE 4-15: DIRECT/INDIRECT ADDRESSING  
Direct Addressing  
Indirect Addressing  
(1)  
from opcode  
7
RP1:RP0  
6
0
0
IRP  
FSR register  
bank select  
location select  
bank select  
location select  
00  
01  
80h  
10  
100h  
11  
00h  
180h  
Not  
Used  
Data  
Memory  
7Fh  
FFh  
17Fh  
1FFh  
Bank 0  
Bank 1 Bank 2  
Bank 3  
For register file map detail see Figure 4-4.  
Note 1:  
The RP1 and IRP bits are reserved, always maintain these bits clear.  
DS30272A-page 24  
1997 Microchip Technology Inc.  
 
 
 
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