PIC16C71X
Applicable Devices 710 71 711 715
FIGURE 11-7: A/D CONVERSION TIMING
BSF ADCON0, GO
(TOSC/2) (1)
1 Tcy
131
130
Q4
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 11-7: A/D CONVERSION REQUIREMENTS
Param Sym Characteristic
No.
Min
Typ†
Max Units
Conditions
130
TAD A/D clock period PIC16C710/711
1.6
2.0
2.0*
3.0*
—
—
—
—
—
µs TOSC based, VREF ≥ 3.0V
µs TOSC based, VREF full range
µs A/D RC mode
PIC16LC710/711
PIC16C710/711
PIC16LC710/711
4.0
6.0
9.5
6.0
9.0
—
µs A/D RC mode
131
132
TCNV Conversion time
(not including S/H time). (Note 1)
TACQ Acquisition time
TAD
Note 2
5*
20
—
—
—
µs
µs The minimum time is the amplifier
settling time. This may be used if the
"new" input voltage has not changed
by more than 1 LSb (i.e., 19.5 mV @
5.12V) from the last sampled voltage
(as stated on CHOLD).
134
135
TGO Q4 to AD clock start
—
TOSC/2§
—
—
—
—
If the A/D clock source is selected as
RC, a time of TCY is added before the
A/D clock starts. This allows the
SLEEPinstruction to be executed.
TSWC Switching from convert → sample time 1.5§
TAD
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 7.1 for min conditions.
DS30272A-page 100
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
