PIC16F62X
10.2.1 CCP PIN CONFIGURATION
10.2
Compare Mode
The user must configure the RB3/CCP1 pin as an out-
put by clearing the TRISB<3> bit.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RB3/CCP1 pin is:
Note: Clearing the CCP1CON register will force
the RB3/CCP1 compare output latch to the
default low level. This is not the data latch.
• driven High
• driven Low
• remains Unchanged
10.2.2 TIMER1 MODE SELECTION
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
FIGURE 10-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
10.2.3 SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
Special event trigger will reset Timer1, but not
set interrupt flag bit TMR1IF (PIR1<0>)
10.2.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
Special Event Trigger (CCP2 only)
Set flag bit CCP1IF
(PIR1<2>)
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
CCPR1H CCPR1L
Q
S
R
Output
Logic
Comparator
match
RB3/CCP1
Pin
TRISB<3>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
TABLE 10-2
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on
all other
resets
Value on
POR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh/8Bh/1
0Bh/18Bh
0000 000x 0000 000u
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0Ch
8Ch
87h
0Eh
0Fh
10h
15h
16h
17h
0000 -000 0000 -000
0000 -000 0000 -000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
PIR1
PIE1
EEIF CMIF
RCIF
TXIF
—
—
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
EEIE CMIF
RCIE
TXIE
PORTB Data Direction Register
TRISB
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1register
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
—
—
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 65
MICROCHIP [ MICROCHIP ]
