PIC16F62X
FIGURE 5-10: BLOCK DIAGRAM OF RB2/TX/CK PIN
VDD
RBPU
weak pull-up
P
VDD
PORT/PERIPHERAL Select(1)
USART TX/CK output
0
1
VDD
Data Bus
RB2/TX/CK
pin
D
Q
Q
P
WR PORTB
CK
VSS
Data Latch
D
Q
Q
WR TRISB
N
CK
TRIS Latch
Vss
RD TRISB
TTL
input
buffer
Peripheral OE(2)
Q
D
RD PORTB
EN
EN
USART Slave Clock in
RD PORTB
Schmitt
Trigger
Note 1: Port/Peripheral select signal selects between port data and peripheral output.
Note 2: Peripheral OE( output enable) is only active if peripheral select is active.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 37