PIC16C745/765
4.2.2.4
PIE1 REGISTER
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 4-4: PERIPHERAL INTERRUPT ENABLE1 REGISTER (PIE1: 8Ch)
R/W-0
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
USBIE
R/W-0
R/W-0
R/W-0
(1)
R
W
U
=
=
=
Readable bit
Writable bit
Unimplemented bit,
read as ‘0’
PSPIE
CCP1IE
TMR2IE TMR1IE
bit7
bit0
-n
=
Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
USBIE: Universal Serial Bus Interrupt Enable bit
1= Enables the USB interrupt
0= Disables the USB interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: PIC16C745 device does not have a parallel slave port implemented; always maintain this bit clear.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 25
MICROCHIP [ MICROCHIP ]
