PIC16C5X
FIGURE 4-2: PIC16C54s/CR54s/C55s
4.0
MEMORY ORGANIZATION
PROGRAM MEMORY MAP
AND STACK
PIC16C5X memory is organized into program memory
and data memory. For devices with more than 512
bytes of program memory, a paging scheme is used.
Program memory pages are accessed using one or
two STATUS register bits. For devices with a data
memory register file of more than 32 registers, a
banking scheme is used. Data memory banks are
accessed using the File Selection Register (FSR).
PC<8:0>
9
CALL, RETLW
Stack Level 1
Stack Level 2
000h
4.1
Program Memory Organization
On-chip
Program
Memory
0FFh
100h
The PIC16C52 has a 9-bit Program Counter (PC)
capable of addressing a 384 x 12 program memory
space (Figure 4-1). The PIC16C54s, PIC16CR54s and
PIC16C55s have a 9-bit Program Counter (PC)
capable of addressing a 512 x 12 program memory
space (Figure 4-2). The PIC16C56s and PIC16CR56s
have a 10-bit Program Counter (PC) capable of
addressing a 1K x 12 program memory space
(Figure 4-3). The PIC16CR57s, PIC16C58s and
PIC16CR58s have an 11-bit Program Counter capable
of addressing a 2K x 12 program memory space
(Figure 4-4). Accessing a location above the physically
implemented address will cause a wraparound.
Reset Vector
1FFh
FIGURE 4-3: PIC16C56s/CR56s
PROGRAM MEMORY MAP
AND STACK
PC<9:0>
10
CALL, RETLW
The reset vector for the PIC16C52 is at 17Fh. A NOP
at the reset vector location will cause a restart at
location 000h. The reset vector for the PIC16C54s,
PIC16CR54s and PIC16C55s is at 1FFh. The reset
vector for the PIC16C56s and PIC16CR56s is at
3FFh. The reset vector for the PIC16C57s,
PIC16CR57s, PIC16C58s, and PIC16CR58s is at
7FFh.
Stack Level 1
Stack Level 2
000h
On-chip Program
Memory (Page 0)
0FFh
100h
1FFh
200h
On-chip Program
Memory (Page 1)
2FFh
300h
FIGURE 4-1: PIC16C52 PROGRAM
MEMORY MAP AND STACK
PC<8:0>
Reset Vector
3FFh
9
CALL, RETLW
Stack Level 1
Stack Level 2
000h
On-chip Program
Memory
Reset Vector
17Fh
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 15
MICROCHIP [ MICROCHIP ]
