PIC16F870/871
.
8.2
Compare Mode
Note: The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
8.3
PWM Mode (PWM)
• Driven low
In pulse width modulation mode, the CCP1 pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit CCP1IF is set.
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
FIGURE 8-2: COMPARE MODE OPERATION
BLOCK DIAGRAM
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Figure 8-3 shows a simplified block diagram of the CCP
module in PWM mode.
Special Event Trigger
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3.
Set flag bit CCP1IF
(PIR1<2>)
CCPR1H CCPR1L
FIGURE 8-3: SIMPLIFIED PWM BLOCK
DIAGRAM
Q
S
R
Output
Logic
Comparator
match
RC2/CCP1
Pin
CCP1CON<5:4>
Duty Cycle Registers
TRISC<2>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
CCPR1L
8.2.1
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
CCPR1H (Slave)
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
Q
R
S
Comparator
RC2/CCP1
(Note 1)
TMR2
8.2.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
8.2.3
SOFTWARE INTERRUPT MODE
or 2 bits of the prescaler to create 10-bit time-base.
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
8.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled). This allows the CCPR1 regis-
ter to effectively be a 16-bit programmable period reg-
ister for Timer1.
1999 Microchip Technology Inc.
Preliminary
DS30569A -page 59
MICROCHIP [ MICROCHIP ]
