PIC16F870/871
FIGURE 3-9: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 3-10: PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 3-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
09h
89h
0Ch
8Ch
9Fh
PORTD Port data latch when written: Port pins when read
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
0000 -111 0000 -111
PORTE
TRISE
PIR1
—
—
—
—
—
—
—
—
RE2
RE1
RE0
IBF
OBF IBOV PSPMODE
PORTE Data Direction Bits
PSPIF ADIF RCIF
PSPIE ADIE RCIE
TXIF
TXIE
—
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIE1
ADCON1 ADFM
—
—
PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 37
MICROCHIP [ MICROCHIP ]
