PIC16F870/871
2.2
Data Memory Organization
2.0
MEMORY ORGANIZATION
There are three memory blocks in each of these
PICmicro® MCUs. The Program Memory and Data
Memory have separate buses, so that concurrent
access can occur, and is detailed in this section. The
EEPROM data memory block is detailed in
Section 4.0.
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1(STATUS<6>) and
RP0 (STATUS<5>) are the bank select bits.
RP<1:0>
00
Bank
0
1
2
3
Additional information on device memory may be found
01
in the PICmicro
(DS33023).
Mid-Range Reference Manual,
10
11
2.1
Program Memory Organization
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.
The PIC16F870/871 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. The PIC16F870/871 devices have 2K
x 14 words of FLASH program memory. Accessing a
location above the physically implemented address will
cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
Note: EEPROM Data Memory description can be
found in Section 4.0 of this Data Sheet
FIGURE 2-1: PIC16F870/871 PROGRAM
MEMORY MAP AND STACK
2.2.1
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR.
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
Interrupt Vector
Page 0
0004h
0005h
On-Chip
Program
Memory
07FFh
0800h
1FFFh
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 11
MICROCHIP [ MICROCHIP ]
