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PIC16C745-I/SO 参数 Datasheet PDF下载

PIC16C745-I/SO图片预览
型号: PIC16C745-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: IC- 8-BIT MCU\n [IC-8-BIT MCU ]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC可编程只读存储器时钟
文件页数/大小: 158 页 / 2499 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16C745/765  
11.4.2 USART SYNCHRONOUS SLAVE  
11.4  
USART Synchronous Slave Mode  
RECEPTION  
Synchronous slave mode differs from the Master mode  
in the fact that the shift clock is supplied externally at  
the RC6/TX/CK pin (instead of being supplied internally  
in master mode). This allows the device to transfer or  
receive data while in SLEEP mode. Slave mode is  
entered by clearing bit CSRC (TXSTA<7>).  
The operation of the synchronous master and slave  
modes is identical, except in the case of the SLEEP  
mode. Also, bit SREN is a don’t care in slave mode.  
If receive is enabled by setting bit CREN prior to the  
SLEEP instruction, a word may be received during  
SLEEP. On completely receiving the word, the RSR  
register will transfer the data to the RCREG register  
and if enable bit RCIE bit is set, the interrupt generated  
will wake the chip from SLEEP. If the global interrupt is  
enabled, the program will branch to the interrupt vector  
(0004h).  
11.4.1 USART SYNCHRONOUS SLAVE  
TRANSMIT  
The operation of the synchronous master and slave  
modes are identical, except in the case of the SLEEP  
mode.  
Steps to follow when setting up a Synchronous Slave  
Reception:  
If two words are written to the TXREG and then the  
SLEEPinstruction is executed, the following will occur:  
1. Enable the synchronous master serial port by  
setting bits SYNC and SPEN and clearing bit  
CSRC.  
a) The first word will immediately transfer to the  
TSR register and transmit.  
b) The second word will remain in TXREG register.  
c) Flag bit TXIF will not be set.  
2. If interrupts are desired, set enable bit RCIE.  
3. If 9-bit reception is desired, set bit RX9.  
4. To enable reception, set enable bit CREN.  
d) When the first word has been shifted out of TSR,  
the TXREG register will transfer the second  
word to the TSR and flag bit TXIF will now be  
set.  
5. Flag bit RCIF will be set when reception is com-  
plete and an interrupt will be generated, if  
enable bit RCIE was set.  
e) If enable bit TXIE is set, the interrupt will wake  
the chip from SLEEP and if the global interrupt  
is enabled, the program will branch to the inter-  
rupt vector (0004h).  
6. Read the RCSTA register to get the ninth bit (if  
enabled) and determine if any error occurred  
during reception.  
7. Read the 8-bit received data by reading the  
RCREG register.  
Steps to follow when setting up a synchronous slave  
transmission:  
8. If any error occurred, clear the error by clearing  
bit CREN.  
1. Enable the synchronous slave serial port by set-  
ting bits SYNC and SPEN and clearing bit  
CSRC.  
2. Clear bits CREN and SREN.  
3. If interrupts are desired, then set enable bit  
TXIE.  
4. If 9-bit transmission is desired, set bit TX9.  
5. Enable the transmission by setting enable bit  
TXEN.  
6. If 9-bit transmission is selected, the ninth bit  
should be loaded in bit TX9D.  
7. Start transmission by loading data to the  
TXREG register.  
1999 Microchip Technology Inc.  
Advanced Information  
DS41124A-page 87