PIC16C745/765
11.2.2 USART ASYNCHRONOUS RECEIVER
two bytes of data to be received and transferred to the
RCREG FIFO and a third byte to begin shifting to the
RSR register. On the detection of the STOP bit of the
third byte, if the RCREG register is still full, then overrun
error bit OERR (RCSTA<1>) will be set. The word in the
RSR will be lost. The RCREG register can be read
twice to retrieve the two bytes in the FIFO. Overrun bit
OERR has to be cleared in software. This is done by
resetting the receive logic (CREN is cleared and then
set). If bit OERR is set, transfers from the RSR register
to the RCREG register are inhibited, so it is essential to
clear error bit OERR if it is set. Framing error bit FERR
(RCSTA<2>) is set if a stop bit is detected as clear. Bit
FERR and the 9th receive bit are buffered the same
way as the receive data. Reading the RCREG, will load
bits RX9D and FERR with new values, therefore it is
essential for the user to read the RCSTA register before
reading RCREG register in order not to lose the old
FERR and RX9D information.
The receiver block diagram is shown in Figure 11-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at FINT.
Once asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit which is cleared by the
hardware. It is cleared when the RCREG register has
been read and is empty. The RCREG is a double buff-
ered register, i.e. it is a two deep FIFO. It is possible for
FIGURE 11-4: USART RECEIVE BLOCK DIAGRAM
FERR
OERR
CREN
SPBRG
RSR Register
MSb
LSb
Baud Rate Generator
RC7/RX/DT
Stop (8)
7
1
0
Start
• • •
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
FIGURE 11-5: ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX (pin)
bit0
bit1
Stop
bit
Stop
bit
bit7/8 Stop
bit
bit0
bit7/8
bit7/8
Rcv shift
reg
Rcv buffer reg
WORD 2
RCREG
WORD 1
RCREG
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 81
MICROCHIP [ MICROCHIP ]
