PIC16C745/765
10.9.3 INTERRUPT STRUCTURE CONCERNS
10.9.3.1 Processor Resources
10.9
USB Firmware Users Guide
10.9.1 INTRODUCING THE USB SOFTWARE
INTERFACE
Most of the USB processing occurs via the interrupt
and thus is invisible to application. However it still con-
sumes processor resources. These include ROM,
RAM, Common RAM, Stack Levels and processor
cycles. This section attempts to quantify the impact on
each of these resources, and shows ways to avoid
conflicts.
Microchip provides a layer of software that handles the
lowest level interface so your application won’t have to.
This provides a simple Put/Get interface for communi-
cation. Most of the USB processing takes place in the
background through the Interrupt Service Routine.
From the application viewpoint, the enumeration pro-
cess and data communication takes place without fur-
ther interaction.
These are the considerations you'll need to take into
account if you write your own Interrupt Service Rou-
tine: Save W, Status, FSR and PCLATH which are the
file registers that may be corrupted by servicing the
USB interrupt.
FIGURE 10-2: USB SOFTWARE INTERFACE
Main Application
We provide a skeleton ISR which will do this for you,
and includes tests for each of the possible ISR bits.
This provides a good place to start from if you haven't
already written your own. See file USB_INT.ASM.
Put
Get
Init
10.9.3.2 Stack Levels
USB Peripheral
The hardware stack on the device is only 8 levels
deep. So the worst case call between the application
and ISR can only be 8 levels. The enumeration pro-
cess requires 6 levels, so it's best if the main applica-
tion holds off on any processing until enumeration is
complete. ConfiguredUSB is a macro that waits until
the enumeration process is complete for exactly this
purpose.
USB
10.9.2 INTEGRATING USB INTO YOUR
APPLICATION
The latest version of the USB interface software is
available on Microchip Technology’s website. See
http://www.microchip.com/
Communicating on USB is similar to communicating
via a hardware USART. The main difference is that a
USART typically works on a single byte at a time,
where USB operates on a buffer of up to 8 bytes at a
time.
10.9.3.3 ROM
The code required to support the USB interrupt,
including the chapter 9 interface calls, but not including
the descriptor tables is about 1kW. The descriptor and
string descriptor tables can each take up to an addi-
tional 256W. The location of these parts is not
restricted, and the linker script may be edited to control
the placement of each part. See the Strings and
Descriptors sections in the linker script
There is one function defined to start the enumeration
process and two additional functions are defined for
moving buffers between the main application and the
USB peripheral. InitUSB initializes the USB peripheral
allowing the host to enumerate the device. Then for
normal data communications, function PutUSB sends
data to the host and function GetUSB receives data
from the host.
10.9.3.4 RAM
With the exception of Common RAM discussed below,
servicing the USB interrupt costs ~40 bytes of RAM in
Bank 2. That leaves all the General Purpose RAM in
banks zero and one, plus half of bank two available for
your application to use.
There's a lot that happens behind the scenes to make
the communication work, but these calls are all an
application needs to communicate on the bus. The
rest is handled on an interrupt basis.
InitUSB initializes the Buffer Descriptor table, and
enables the USB interrupt so enumeration can begin.
The actual enumeration process occurs automatically,
driven by the host and interrupt service routine. The
macro ConfiguredUSB waits until the device is in the
CONFIGURED mode and ready to go. The time
required to enumerate is completely dependent on the
host and bus loading.
10.9.3.5 Common RAM usage
The PIC16C745/765 has 16 bytes of common RAM.
These are the last 16 addresses in each bank and all
refer to the same 16 bytes of memory without regard
to which register bank is currently addressed by the
RP0 and RP1 bits.
These are particularly useful when responding to inter-
rupts. When an interrupt occurs, the ISR doesn't
immediately know which bank is addressed. With
devices that don't support common RAM, the W regis-
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 71
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