PIC16C745/765
10.5.1.5 Status Register (USTAT)
USB transaction is performed before the TOK_DNE
interrupt is serviced the USB will store the status of the
next transaction in the STAT FIFO. Thus, the STAT reg-
ister is actually a four byte FIFO which allows the MCU
to process one transaction while the SIE is processing
the next. Clearing the TOK_DNE bit in the INT_STAT
register causes the SIE to update the STAT register
with the contents of the next STAT value. If the data in
the STAT holding register is valid, the SIE will immedi-
ately reassert the TOK_DNE interrupt.
The USB Status Register reports the transaction sta-
tus within the USB. When the MCU recognizes a
TOK_DNE interrupt, this register should be read to
determine the status of the previous endpoint commu-
nication. The data in the status register is valid when
the TOK_DNE interrupt bit is asserted.
The USTAT register is actually a read window into a
status FIFO maintained by the USB. When the USB
uses a BD, it updates the status register. If another
REGISTER 10-5: USB STATUS REGISTER (USTAT: 194h)
U-0
U-0
U-0
R-X
R-X
R-X
IN
U-0
U-0
ENDP1
ENDP0
—
—
—
—
—
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
X = Don’t care
bit 7-5: Unimplemented: Read as ’0’.
bit 4-3: ENDP<1:0>: These bits encode the endpoint address that received or transmitted the previous token.
This allows the microprocessor to determine which BDT entry was updated by the last USB transaction.
bit 2:
IN: This bit indicates the direction of the last BD that was updated.
1= The last transaction was an IN TOKEN
0= The last transaction was an OUT or SETUP TOKEN
bit 1-0: Unimplemented: Read as ’0’.
DS41124A-page 64
Advanced Information
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
